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HT16514
Dot Character VFD Controller & Driver
Features
* Logic voltage: 2.7V~5.5V * High voltage: 60V (max.) * Provides a driving segment for cursor display * Display contents: - 16 columns by 2 (1) rows + 32 (16) cursors - 20 columns by 2 (1) rows + 40 (20) cursors - 24 columns by 2 (1) rows + 48 (24) cursors * Supports display output (80-segment & 24-grid) * Parallel data input/output (switchable 4 bit or 8 bit) or
(48 units)
* Alphanumeric and symbolic display through built-in
ROM
* 808-bit display RAM * On chip ROM (58 dot), in total 248 characters,
serial data input/output
* Built-in oscillation circuit * 144-pin LQFP package
plus 8 user-defined characters
* Customized ROM acceptable
Applications
* Consumer products panel function control * Industrial measuring instrument panel function * Other similar application panel function control
control
General Description
The HT16514 is a Vacuum Fluorescent Display, VFD controller/driver with dot matrix VFD display. It consists of 80 segment output lines and 24 grid output lines. It can display up to 16C2L, 20C2L, 24C2L. The HT16514 has a character generator ROM which stores up to 24858 dot characters. The HT16514 has serial/parallel interface. This VFD controller/driver is ideal as an MCU peripheral device.
Ordering Information
Part Number HT16514-001 HT16514-002 Package Information 144-pin plastic LQFP (Fine pitch) (2020), standard ROM (ROM code: 001) 144-pin plastic LQFP (Fine pitch) (2020), standard ROM (ROM code: 002)
Rev. 1.00
1
October 4, 2006
HT16514
Block Diagram
TESTO TESTI RL2 RL1 DLS DS1 DS0 MPU IM CS R S,ST R,W (W R ) S I, S O D B0~D B3 D B4~D B7 4 8 4 8 In s tr u c tio n R e g is te r ( IR ) In s tr u c tio n D e c o rd e r 7 7 E (R D ), S C K I/O In te rfa c e 8 7 8 8 8 C r u s o r B lin k C ir c u it 7 A d d re s s C o u n te r 8 DDRAM ( 8 0 x 8 B its ) 7 7 T im in g G e n e ra to r 4 24 24 2 4 - B it S h ift R e g is te r G1 G r id D r iv e r G 24 D a ta R e g is te r (D R ) P a r a lle l to S e r ia l D a ta C o n v e rte r 5 5 8 0 - B it O u tp u t L a tc h & R e g is te r 80
CGRAM ( 8 x 5 x 8 B its )
CGROM ( 2 4 8 x 5 x 8 B its )
Segm ent D r iv e r
S1 S80
RESET
RESET C ir c u it
OSCI OSCO XOUT OSC
VDD
LG ND
VH
PGND
SD O ,SLK,C L,LE
Pin Assignment
S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70
NC S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 G 24 G 23 G 22 G 21 G 20 G 19 G 18 G 17 G 16 G 15 G 14 G 13 G 12 G 11 G 10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC
108 109
73 72
H T16514 1 4 4 L Q F P -A
144 1
VH
36
37
NC S3 S3 S3 S3 S3 S2 S2 S2 S2 S2 S2 S2 S2 S2 S2 S1 S1 S1 S1 S1 S1 S1 S1 S1 S1 S9 S8 S7 S6 S5 S4 S3 S2 S1 NC 4 3 2 1 0 9 8 7
6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
VH PGN LG N TES CLK SDO LE CL RL2 RL1 CS MPU IM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 S I, S E (R RS, R ,W DS0 DS1 DLS TES RES OSC OSC XOU VDD PGN O D ), S C K ST (W R ) TI ET I O D D TO D T
Rev. 1.00
2
October 4, 2006
HT16514
Pin Description
Pin Name I/O Description Logic System (Microprocessor Interface) When parallel mode is selected, this pin is utilized to select the register, either Instruction Register or Data Register. 0: IR (Instruction Register) 1: DR (Data Register) When serial mode is selected, this pin performs strobe input. Data can be set as input when this signal goes 0. During the next rising edge of this signal, command processing is performed. When M68 parallel mode is selected (E), this pin is write enable. Writes data at the falling edge. When i80 parallel mode is selected (RD), this pin is read enable. When this pin is Low, data is output to the data Bus. When Serial mode is selected, this pin is shift clock input, data will be written at the rising edge. When this pin is Low, the device is active. Connected to an external resistor to generate an oscillation frequency. Oscillator signal output pin When M68 parallel mode is selected (R, W), this pin is data mode select pin (0: write, 1: read). When i80 parallel mode is selected (WR), this pin is a write enable pin. Data will be written at rising edge signal. When serial mode is selected, connect this pin to Hi or Low. Read or Write is chosen by instruction. When serial mode is selected, this pin is used as I/O pin. When parallel mode is selected, this pin needs to be connected to Hi or Low.
RS, ST
I
E (RD), SCK
I
CS OSCI OSCO XOUT
I I O O
R, W (WR)
I
SI, SO
I/O
DB0~DB7
When parallel mode is selected, these pins are used as I/O pins. I/O Data are stored sequentially, the first bit which is sent to the HT16514 is MSB. If 4 bits mode is selected, only DB4~DB7 are used. I I Initialize all the internal register and commands. All segments and digits are fixed PGND. Set the duty ratio. Duty ratio will determine the number of grid. The relationship between duty ratio and these pins is shown in Table 1-1. Select interface mode (parallel mode or serial mode) 0: Serial mode 1: Parallel mode In parallel mode, instruction will determine the length of word. Select interface mode (i80 type CPU mode or M68 type CPU mode) 0: i80 type CPU mode 1: M68 type CPU mode Select number of display line when power ON reset or resetting. 0: Select 1 line (N=0), N is display line select flag in Function set command. 1: Select 2 line (N=1) Set segment outputs pin assignment. The selection table is listed as Table 1-2 & Table 1-7 0 or open: Normal operation mode 1: Test mode For IC testing only, leave this pin open.
RESET DS0, DS1
IM
I
MPU
I
DLS RL1, RL2 TESTI TESTO
I I I O
Logic System ( To External Extension Driver) SDO SLK O O Serial data output for extension digit driver. Shift clock pulse for extension digit driver. Active during rising edge
Rev. 1.00
3
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HT16514
Pin Name CL LE Output Pins G1~G24 S1~S80 Power System VDD LGND VH PGND 3/4 3/4 3/4 3/4 Pins for logic circuit LGND is ground pin for logic circuit Power supply pins for VFD driver circuit PGND is ground pin for VFD driver circuit O O High-voltage output, grid output pins. High-voltage output, segment output pins. I/O O O Description Clear signal for extension digit driver, active low. The digit data stored in the latch register of the extension driver are output when this signal is Hi, if this signal is Low, extension driver outputs are Low. Latch enable signal for extension digit driver.
Table 1-1. Duty Ratio Setting DS0 0 0 1 1 Note: DS1 0 1 0 1 Duty Ratio 1/16 (# of grid = 16) 1/24 (# of grid = 24) 1/20 (# of grid = 20) 1/40 (# of grid = 40)*
* When setting to 1/40 duty mode, use the external extension grid driver.
Table 1-2. Segment Setting: 2 Line Display (N=1) RL1 0 0 1 1 RL2 0 1 0 1 Table No. Table 1-3 Table 1-4 Table 1-5 Table 1-6
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HT16514
Table 1-3. The Number Of Segment Pins 1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VH PGND VDD XOUT OSCO OSCI RESET TESTI DLS DS1 DS0 R, W (WR) RS, ST E (RD), SCK SI, SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU CS RL1 RL2 CL LE SDO SLK TESTO LGND PGND VH No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name NC S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 NC No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name NC S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC
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HT16514
Table 1-4. The Number Of Segment Pins 2 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VH PGND VDD XOUT OSC OSCI RESET TESTI DLS DS1 DS0 R, W (WR) RS, ST E (RD), SCK SI, SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU CS RL1 RL2 CL LE SDO SLK TESTO LGND PGND VH No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name NC S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 NC No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name S6 S5 S4 S3 S2 S1 S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name NC S71 S72 S73 S74 S75 S76 S77 S78 S79 S80 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC
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HT16514
Table 1-5. The Number Of Segment Pins 3 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VH PGND VDD XOUT OSCO OSCI RESET TESTI DLS DS1 DS0 R, W (WR) RS, ST E (RD), SCK SI, SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU CS RL1 RL2 CL LE SDO SLK TESTO LGND PGND VH No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name NC S41 S42 S43 S44 S45 S46 S47 S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 S64 S65 S66 S67 S68 S69 S70 S71 S72 S73 S74 NC No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name S75 S76 S77 S78 S79 S80 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name NC S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC
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7
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HT16514
Table 1-6. The Number Of Segment Pins 4 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VH PGND VDD XOUT OSCO OSCI RESET TESTI DLS DS1 DS0 R, W (WR) RS, ST E (RD), SCK SI, SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU CS RL1 RL2 CL LE SDO SLK TESTO LGND PGND VH No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name NC S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 S49 S48 S47 NC No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name NC S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC
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8
October 4, 2006
HT16514
Table 1-7. Segment Setting: 1 Line Display (N=0) RL1 Dont care Dont care RL2 0 1 Table No. Table 1-8 Table 1-9
Table 1-8. The Number Of Segment Pins 5 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VH PGND VDD XOUT OSCO OSCI RESET TESTI DLS DS1 DS0 R, W (WR) RS, ST E (RD), SCK SI, SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU CS RL1 RL2 CL LE SDO SLK TESTO LGND PGND VH No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name NC S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 NC No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name S35 S36 S37 S38 S39 S40 Dont use No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC Name NC Dont use
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9
October 4, 2006
HT16514
Table 1-9. The Number Of Segment Pins 6 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name VH PGND VDD XOUT OSCO OSCI RESET TESTI DLS DS1 DS0 R, W (WR) RS, ST E (RD), SCK SI, SO DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 IM MPU CS RL1 RL2 CL LE SDO SLK TESTO LGND PGND VH No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name NC S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 NC No. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name S6 S5 S4 S3 S2 S1 Dont use No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 NC Name NC Dont use
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HT16514
HT16514 Connect to VFD as Below Figure
Rev. 1.00
11
October 4, 2006
HT16514
Approximate Internal Connections
(M P U ) (R S , S T ) (C S ) (D L S ) (D S 0 ) (D S 1 ) (IM ) (R L 1 ) (R L 2 ) (T E S T I) S L K , E (R D ), R E S E T , (R , W /W R ) V
DD
SD O ,SLK C L,LE,TESTO
V
DD
V
DD
LG N D LG N D
LG N D
S1~S80,G 1~G 24
O S C O , O S C I, X O U T
D 0 ~ D 7 , S I, S O
V
VH XOUT OSCO
DD
PGND
OSCI
Absolute Maximum Ratings
Logic Supply Voltage .................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Driver Output Voltage............................VSS-0.3V to VH Driver Output Current (Total) ...................500 (Est.) mA Operating Temperature ...........................-40C to 85C Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Driver Supply Voltage .................VSS-0.3V to VSS+80V Output Voltage...........................VSS-0.3V to VDD+0.3V Driver Output Current .........................................50mA Storage Temperature ............................-55C to 125C
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12
October 4, 2006
HT16514
D.C. Characteristics
Symbol VDD VH IDD IH ILOH ILOL IIH IP VIH1 VIL1 VIH2 VIL2 VOH1 VOL1 VOH21 VOH22 VOH2G VOL2 Hi-level Output Voltage Parameter Logic Supply Voltage VFD Supply Voltage Operating Current Operating Current VDD 3/4 3/4 VH=50V, VSS=VLGND=VPGND=0V, Ta=-40C~85C Test Conditions Conditions 3/4 3/4 Min. 2.7 20 3/4 3/4 3/4 3/4 5 5 0.7VDD 0 0.8VDD 0 Typ. 5 3/4 3/4 3/4 3/4 3/4 3/4 125 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 5.5 50 1000 500 1 -1 500 280 VDD 0.3VDD VDD 0.2VDD VDD VSS+0.5 3/4 3/4 3/4 5 Unit V V mA mA mA mA mA mA V V V V V V V V V V
2.7V~5.5V No load, CPU Non-access 2.7V~5.5V No load Logic except DB0~DB7, SI, SO, VIN/OUT=VDD
Hi-level Leakage Current 2.7V~5.5V
Hi-level Leakage Current 2.7V~5.5V Logic VIN/OUT=VSS Hi-level Input Current Pull-up MOS Current H Input Voltage 1 L Input Voltage 1 H Input Voltage 2 L Input Voltage 2 Hi-level Output Voltage 2.7V~5.5V TEST, VIN=VDD 2.7V~5.5V DB0~DB7, SI, SO 3/4 3/4 3/4 3/4 2.7V~5.5V Except E, SCK, RESET, R, W (WR) Except E,SCK, RESET, R, W (WR) E, SCK, RESET, R, W (WR) E, SCK, RESET, R ,W (WR)
DB0~DB7, SI,SO, SDO, SLK, VDD-0.5 LE, CL, IOL1= -0.1mA DB0~DB7, SI,SO, SDO, SLK, LE, CL, IOL1= 0.1mA S1~S80, IOH2= -0.5mA 0 48 46 45 3/4
Low-level Output Voltage 2.7V~5.5V
2.7V~5.5V S1~S80, IOH2= -1mA G1~G24, IOH2= -15mA
Low-level Output Voltage 2.7V~5.5V S1~S80, G1~G24, IOL2= 1mA
A.C. Characteristics
Symbol fOSC fC tR1 tR2 tF Parameter Oscillation Frequency Oscillation Frequency Rise Time Test Conditions VDD
VH=50V, VSS=VLGND=VPGND=0V, Ta=-40C~85C Min. 392 350 3/4 3/4 3/4 Typ. 560 560 3/4 3/4 3/4 Max. 728 750 2.5 0.25 2 Unit kHz kHz ms ms ms
Conditions
2.7V~5.5V ROSC=56kW 2.7V~5.5V OSCI external clock 2.7V~5.5V CL= 50pF, S1~S80 2.7V~5.5V CL=50pF, G1~G24 2.7V~5.5V CL= 50pF, S1~S80, G1~G24
Fall Time
Switching Timing
tF 90% Sn,G n 10% 10% tR 1 , tR
2
90%
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HT16514
Timing Conditions 1 for M68-Type for Parallel Mode, Write Symbol Parameter Test Conditions VDD 4.5V~5.5V Enable Cycle Time 2.7V~4.5V 4.5V~5.5V Enable Pulse Width High 2.7V~4.5V 4.5V~5.5V Enable Pulse Width Low 2.7V~4.5V ((RS), (R, W), (CS)) 3/4 (E) Setup Time ((RS), (R, W)) 3/4 (E) Hold Time (CS) 3/4 (E) Hold Time 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V Write Data Setup Time 2.7V~4.5V 4.5V~5.5V Write Data Hold Time 2.7V~4.5V 4.5V~5.5V Reset Pulse Width 2.7V~4.5V RS, R, W, CS (R) E E 450 20 60 10 20 20 40 80 195 10 10 500 500 E 450 230 Conditions E (R) E Min. 500 1000 230 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Ta=25C Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Ta=25C Test Conditions VDD 4.5V~5.5V Enable Cycle Time 2.7V~4.5V 4.5V~5.5V Enable Pulse Width High 2.7V~4.5V 4.5V~5.5V Enable Pulse Width Low 2.7V~4.5V ((RS), (R, W), (CS)) 3/4 (E) Setup Time ((RS), (R, W)) 3/4 (E) Hold Time (CS) 3/4 (E) Hold Time 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V Read Data Setup Time 2.7V~4.5V 4.5V~5.5V Read Data Hold Time 2.7V~4.5V RS, R, W, CS (R) E E 450 20 60 10 30 20 40 3/4 3/4 5 5 E 450 230 Conditions E (R) E Min. 500 1000 230 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 160 360 3/4 3/4 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCYCLE
PWEH
PWEL
tAS
tAH
E (R) RS, R, W
tCH
E (R) CS
tDS
Data (R) E
tDH
E (R) Data
tWRE
3/4
M68-Type for Parallel Mode, Read Symbol Parameter
tCYCLE
PWEH
PWEL
tAS
tAH
E (R) RS, R, W
tCH
E (R) CS
tDD
Data (R) E
tDHr
E (R) Data
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HT16514
Parallel Mode (M68 Input)
RS
R,W
tA
S
tA
H
CS PW
EH
PW
EL
E
tD
S
tD
HR
DB0 DB7
V a lid D a ta tC
YCE
Parallel Mode (M68 Output)
RS
R,W tA
S
tA
H
CS PW
EH
PW
EL
E
tD
D
tD
H
DB0 DB7
V a lid D a ta tC
YCE
Note:
The input signal rising time and falling time (tf, tr) is specified at 15ns or less. All timing is specified using 20% and 80% of VDD as the reference. PWEH is specified as the overlap between CS being L and E.
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Timing Conditions 2 for i80-Type, Parallel Mode Symbol Parameter Test Conditions VDD 4.5V~5.5V RS Hold Time 2.7V~4.5V tCH8 4.5V~5.5V CS Hold Time 2.7V~4.5V tRS8 4.5V~5.5V RS, CS Setup Time 2.7V~4.5V tCYC8 4.5V~5.5V System Cycle Time 2.7V~4.5V tCCLW Control L Pulse Width (WR) 4.5V~5.5V WR 2.7V~4.5V 4.5V~5.5V RD 2.7V~4.5V 4.5V~5.5V WR 2.7V~4.5V 4.5V~5.5V RD 2.7V~4.5V 4.5V~5.5V Data Setup Time 2.7V~4.5V tDH8 4.5V~5.5V Data Hold Time 2.7V~4.5V tACC8 4.5V~5.5V RD Access Time 2.7V~4.5V tOH8 4.5V~5.5V Output Disable Time 2.7V~4.5V tWRE 4.5V~5.5V Reset Pulse Width 2.7V~4.5V 3/4 DB0~DB7, CL=100pF DB0~DB7, CL=100pF DB0~DB7 20 3/4 3/4 5 5 500 500 DB0~DB7 60 10 200 30 200 100 200 100 50 70 3/4 RS, CS 30 200 600 30 CS 40 10 RS 20 20 Conditions Min. 10 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 70 140 3/4 3/4 3/4 3/4 Ta=25C Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRH8
tCCLR
Control L Pulse Width (RD)
tCCHW
Control H Pulse Width (WR)
tCCHR
Control H Pulse Width (RD)
tDS8
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Parallel Mode (i80)
RS tR
H8
tf CS tR
S8
tr
tC tC
CLR
YC8
, tC
CLW
W R,RD tf tD D B0~D B7 ( W r ite ) tA D B0~D B7 (R e a d )
CC8 S8
tC tD
H8
CHR
, tC
CHW
tO
H8
Note:
The input signal rising time and falling time (tf, tr) is specified at 15ns or less. All timing is specified using 20% and 80% of VDD as the reference. tCCLW and tCCLR are specified as the overlap between CS as L and WR and RD at the L level.
Timing Conditions 3 for Serial Mode Symbol tCYK tWHK tWLK tHSTBK tDS tDK tDKSTB tWSTB tWAIT tODO Parameter Shift Clock Cycle Test Conditions VDD 4.5V~5.5V 2.7V~4.5V SCK Conditions Min. 500 1000 200 300 200 300 100 150 100 150 100 150 500 750 500 750 1 1 3/4 3/4 Typ. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Max. 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 150 300
Ta=25C Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns
High-level Shift Clock Pulse 4.5V~5.5V SCK Width 2.7V~4.5V Low-level Shift Clock Pulse 4.5V~5.5V SCK Width 2.7V~4.5V Shift Clock Hold Time 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V STD (R) SCK Data (R) SCK SCK (R) Data SCK (R) ST 3/4 8th CLK (R) 1st CLK ST (R) Data
Data Setup Time
Data Hold Time
ST Hold Time
ST Pulse Width
Wait Time
Output Data Delay Time
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Symbol tODH tWRE Parameter Output Data Hold Time Test Conditions VDD 4.5V~5.5V 2.7V~4.5V 4.5V~5.5V 2.7V~4.5V Conditions SCK (R) Data 3/4 Min. 5 5 500 500 Typ. 3/4 3/4 3/4 3/4 Max. 3/4 3/4 3/4 3/4 Unit ns ns ns ns
Reset Pulse Width
Serial Mode (Input)
tW ST tH
STBK STB
tC tW
HK
YK
tD tW
LK
KSTB
SCK
tD
S
tD
H
SI
Serial Mode (Output)
tW ST tH
STBK STB
tC tW
HK
YK
tD tW
LK
KSTB
SCK tO
DO
tO
DH
SO
AC Measurement Point
V In p u t V O u tp u t R eset
OH IH
V
IL
V
OL
RESET tW
RE
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Timing Condition for interface: M68, i80 and Serial Power On Reset Symbol tRES ttrDD tOFF Parameter Resetting Time VDD Rising Time VDD OFF Width
t trD
D
Ta=25C Min. 100 1 1 Typ. 3/4 3/4 3/4 Max. 3/4 3/4 3/4 Unit ms ms ms
Test Conditions VDD 2.7V~4.5V 2.7V~4.5V 2.7V~4.5V
tR 4 .5 V
ES
Conditions 3/4 3/4 3/4
V
DD
0 .2 V tO
FF
In te rn a l R eset T im e
RESET Timing Symbol tRSTD tOFF tRST Parameter Delay Time After Reset VDD Off Time RST/Pulse Width Low Test Conditions VDD 5V 5V 5V Conditions 3/4 3/4 3/4 Min. 100 1 500 Typ. 3/4 3/4 3/4 Max. 3/4 3/4 3/4 Unit ms ns ns
VCC
4 .5 V 0 .2 V
tO
FF
tR
STD
R S,STB
Power Supply Connection Sequence
* Connect the PGND and LGND externally to have an
equal potential voltage
* To avoid faulty connection, turn on the driver power
V o lta g e
supply (VH) after turning on the logic power supply (VDD). Then turn off the logic power supply (VDD) after turning off the driver power supply (VH).
V
* If the power connection sequence recommended by
H
V
DD
Holtek is not followed, theres a possibility that the internal logic transistors may be damaged.
T im e
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Functional Description
CPU Interface HT16514 have 4 or 8-bit parallel interface or serial interface. These modes are selected by IM pin.
* IM=0: Serial mode * IM=1: Parallel mode
CPU Interface Table IM 0 1 CS CS CS RS, ST ST RS E (RD), SCK SCK E (RD) R, W (WR) Note R, W (WR) MPU Note MPU SI, SO SI, SO Note DB0~DB7 Note DB0~DB7
Note: Keep this pin Hi or Lo. Registers (IR, DR) The HT16514 has two 8-bit registers, namely, an instruction register (IR) and a data register (DR). The IR register stores instruction code such as display clear and cursor shift. It also contains address information for display data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU. The DR temporarily stores data to be written into or read from the DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into the DDRAM or CGRAM by internal operation. The DR is also used for data storage when reading data from the DDRAM or CGRAM. When the address information is written into the IR, data is read and then stored into the DR from the DDRAM or CGRAM by internal operation. Data transfer between the MPU is completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is sent to the DR for the next read from the MPU. These two registers can be selected by the register selector (RS) signal, (Refer to CPU Interface table). Registers (IR, DR) Table Common RS 0 0 1 1 M68 R, W 0 1 0 1 RD 1 0 1 0 i80 Register Selection WR 0 1 0 1 Write IR data during internal operation (display clear, etc.) Read data to be busy flag (DB7) and address counter (DB6~DB0) Write DR data (DR(R)DDRAM, CGRAM) Read DR data (DDRAM, CGRAM(R)DR)
Busy Flag (Read BF Flag) Busy flag data (DB7) is always output as 0. Address Counter (AC) The Address counter (AC) assigns address to both DDRAM and CGRAM. When an instruction address is written into the IR, the address information is sent from the IR to the AC. Selection of either DDRAM or CGRAM is also determined concurrently by the instruction. After writing into (or read from) the DDRAM or CGRAM, the AC is automatically incremented by 1 (or decremented by 1). The cursor position are then output to DB0~DB6 when RS=0 and R, W=1 (Refer to Registers (IR, DR) Table).
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Display Data RAM (DDRAM) The Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended capacity is 808 bits or 80 characters. The area in the DDRAM that is not used for display can be used as general data RAM. Refer to DDRAM address table for the relationships between DDRAM address and positions on the VFD. The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal. DDRAM Address Table High Order Bits AC6 AC5 Hexadecimal Example: DDRAM address 3FH 0 1 3
* 1-line display (N=0)
Low Order Bits AC4 AC3 AC2 AC1 AC0
Hexadecimal
1
1
1 F
1
1
Display Position (Digit) DDRAM Address (Hexadecimal) When there are fewer than 80 display characters, the display begins at the head position. For example, if using only one HT16514, 24 characters are displayed. When display shift operation is performed, the DDRAMaddress shifts as shown in the following table. Example: 1-line by 24-character Display Table Display Position (Digit) DDRAM Address (Hexadecimal) For Shift Left 01 02 03 04 05 06 17 18 1 00 2 01 3 02 4 03 5 04 6 05 23 16 24 17 1 00 2 01 3 02 4 03 5 04 6 05 79 4E 80 4F
For Shift Right
4F
00
01
02
03
04
15
16
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* 2-line display (N=1)
Display Position (Digit) DDRAM Address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 39 26 66 40 27 67
When the number of display character is less than 402 lines, the 2 lines are displayed from the head. The first line end address and the second line start address are not consecutive. For example, if using only one HT16514, 24 characters 2 lines are displayed. When display shift operation is performed, the DDRAM address shifts as shown in the following table. Example: 2-line by 24-character Display Table Display Position (Digit) DDRAM Address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 5 04 44 6 05 45 23 16 56 24 17 57
01 For Shift Left 41
02 42
03 43
04 44
05 45
06 46
17 57
18 58
27 For Shift Right 67
00 40
01 41
02 42
03 43
04 44
15 55
16 56
* 40 Characters2 line display
The DDRAM stores the character code of each character being displayed on the VFD. Valid DDRAMaddresses are 00H to 27H and 40H to 67H. The DDRAMnot used for display characters can be used as general purpose RAM. The tables below show the relationship between the DDRAMaddress and the character position on the VFD display shift as shown in the following table. Example: 2-line by 40-character Display Table Display Position (Digit) DDRAM Address (Hexadecimal) 1 00 40 2 01 41 3 02 42 4 03 43 23 16 56 24 17 57 25 18 58 39 26 66 40 27 67
00 For Shift Left 41
01 42
02 43
03 44
17 57
18 58
19 59
27 57
00 40
27 For Shift Right 67
00 40
01 41
02 42 HT16514 Display
15 55
16 56
17 57
25 65 Extension Driver Display
26 66
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* Character Generator ROM (CGROM)

CGROM for generating character patterns of 58 dots from 8-bit character codes, generates 248 type of character patterns. The character codes are shown on the following page. Character codes 00H to 0FH are allocated to the CGRAM
Character Code Table 1 (ROM Code: 001) Rev. 1.00 23 October 4, 2006
HT16514
Character Code Table 2 (ROM Code: 002)
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Character Generator RAM (CGRAM) The CGRAM stores the pixel information (1=pixel on, 0=pixel off) for the eight user-define 58 characters. Valid CGRAM addresses are 00H to 3FH. CGRAM not used to defined characters can be used as general purpose RAM. Character codes 00H~07H (or 08H~0FH) are assigned to the user-defined characters (see section 5.0 character font tables). The table below shows the relationship between the character codes, CGRAM addresses, and CGRAM data for each user-defined character. Relationship between CGRAM address and character code (DDRAM) and 57 (with cursor) dot character patterns (CGRAM)
C h a ra c te r C o d e (R A M
H ig h O r d e r B it Low
D a ta )
CGRAM
H ig h O r d e r B it
A d d re s s A2A1A0
Low O r d e r B it
CGRAM
H ig h O r d e r B it
D a ta
Low O r d e r B it
D7D6D5D4D3D2D1D0
O r d e r B it
A5A4A3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0
D7D6D5D4D3D2D1D0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 X 0 0 X 0 0 1 0 0 X 0 0 1 0 0 X 0 0 1 0 0 0 C u r s o r P o s itio n X 0 0 1 0 X 0 0 1 0 0 X 0 X 1 0 1 0 0 X X 1 1 0 1 0 0 1 0 0 X 1 0 0 0 0 1 0 C h a ra c te r P a tte rn (2 ) 1 X 1 0 0 0 1 X 1 1 X 1 0 1 0 0 1 X 1 0 0 1 0 1 0 0 0 0 1 1 1 C h a ra c te r P a tte rn (1 ) C u r s o r P o s itio n 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 X X X X X X X
X 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0 X X X X X X X
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1
0
1 1 1 1 1 1 1 1
0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 X X X X X X X
X 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1
0 X X X X X X X
X X X X X X X X
X X X X X X X X
X 1 1 1 1 1 1 1 1
0 0 0 1 0 0 0 1 1 0 1 0 1 0 0
0 0 1 0 0 0 1 0 1
1 0 0 0 0 0 1 1 C u r s o r P o s itio n C h a ra c te r P a tte rn (8 )
Note:
X means dont care Character code bits 0~2 correspond to CGRAM address bits 3~5 (3 bits: 8 types) CGRAM address bits 0~2 designate character pattern line position. The 8th line is the cursor position and its display is formed by a logical OR with the cursor. Maintain the 8th line data, corresponding to the cursor display position at 0 as the cursor display. If the 8th line data is 1, 1 bit will light up the 8th line regardless of the cursor presence. Character pattern row position corresponds to CGRAM data bits 0~4 (bit 4 being at the left). CGRAM character patterns are selected when character code bits 4~7 are all 0. However, since character code bit 3 has no effect, the N display example above can be selected by either character code 00H or 08H. 1 for CGRAM data corresponds to display selection and 0 to no selection.
Timing Generation Circuit Timing generation circuit generates timing signals for the operation of internal circuit such as DDRAM, CGRAM and CGROM. The RAM reads the timing for display and the internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interference, such as flickering, in areas other than the display area.
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VFD Driver Circuit VFD driver circuit consists of 24 grid signal drivers and 80 segment signal drivers. When the character font and number of digits are selected by hardware (DS0, DS1) at power on, the required grid signal drivers automatically output drive waveforms, while the other grid signal driver continue to output non-selection waveforms. Sending serial data is latched when the display data character pattern corresponds to the last address of the display data RAM (DDRAM). Since serial data is latched when the display data character pattern corresponds to the starting address enters the internal shift register, the HT16514 drives from the head display. Cursor/Blink Control Circuit Cursor/blink control circuit generates the cursor or character blinking. The cursor or the blinking will appear with the digit located at the display data RAM (DDRAM) address set in the address counter (AC). For example, when the address counter is 08H, the cursor position is displayed at DDRAM address 08H.
Cursor/Blink Control Table
1-line Display
2-line Display Note: The cursor or blinking appears when the address counter (AC) selects the character generator RAM (CGRAM). However, the cursor and blinking become meaningless when the cursor or blinking is displayed in the meaningless position when AC is a CGRAM address.
Interface With CPU Mode
* Parallel Data Transfer M68 (IM=1, MPU=1)
This IC can interface (data transfer) with the CPU in 4 or 8 bits in M68 interface. However, the internal registers consist of 8 bits. Using the DB4 to DB7 twice must perform data transfer in 4 bits. When using 4-bit parallel data transfer, DB0 to DB3 pins remain Hi or Low. The transfer order is initially from the higher 4 bits (D4 to D7) then followed by the lower 4 bits (D0 to D3). BF checks are performed before transferring the higher 4 bits. BF checks are not required before transferring the lower 4 bits.
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4-bit data transfer (M68)
RS
R,W
E
DB7 DB6 DB5 DB4
IR 7 IR 6 IR 5 IR 4 W r ite In s tr u c tio n
IR 3 IR 2 IR 1 IR 0
IR 7 IR 6 IR 5 IR 4 W r ite In s tr u c tio n
IR 3 IR 2 IR 1 IR 0
B F = "0 " IR 6 IR 5 IR 4 Read In s tr u c tio n
IR 3 IR 2 IR 1 IR 0
D7 D6 D5 D4 W r ite D a ta
D3 D2 D1 D0
8-bit data transfer (M68)
RS
R,W
E
DB7
IR 7
IR 7
B F = "0 "
D7
DB6
IR 6
IR 6
IR 6
D6
DB0
IR 0 W r ite In s tr u c tio n
IR 0 W r ite In s tr u c tio n
IR 0 Read In s tr u c tio n
D0 W r ite D a ta
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Parallel mode for i80 (IM=1, MPU=0) When setting IM=1, MPU=0, i80 is selected. In the HT16514, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to internal data bus. There is a certain restriction in the read sequence of this display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read for the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is selected. This relationship is shown in the following figure.
W r itin g M P U WR
DATA N
N+1
N+2
N+3
In te r n a l T im in g BUS H o ld e r
L a tc h
N
N+1
N+2
N+3
W r ite S ig n a l
R e a d in g M P U WR
RD
DATA N
N
n
n+1
In te r n a l T im in g A d d re s s P re s e t Read S ig n a l C o lu m n A d d re s s BUS H o ld e r N A d d re s s S e t #n Dum m y Read P re s e t N In c re m e n t N + 1 N+2
n D a ta R e a d #n
n+1
n+2 D a ta R e a d #n+1
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Serial Mode In the synchronous serial interface mode, instructions and data are sent between the host and the module using 8-bit bytes. Two bytes are required per read/write cycle and are transmitted MSB first. The start byte contains 5 high bits, the Read/Write (R/W) control bit, the Register Select (RS) control bit, and a low bit. The subsequent byte contains the instruction/data bits. The R/W bit determines whether the cycle is a read (high) or a write (low) cycle. The RS bit is used to identify the second byte as an instruction (low) or data (high). This mode uses the strobe (ST) control signal, Serial Clock (SCK) input, and Serial I/O (SI/SO) line to transfer information. In a write cycle, bits are clocked into the module on the rising edge of SCK. In a read cycle, bits in the start byte are clocked into the module on the rising edge of SCK. After a minimum wait time, each bit in the instruction/data byte can be read from the module after each falling edge of SCK. Each read/write cycle begins on the falling edge of ST and ends on the rising edge. To be a valid read/write cycle, the ST must go high at the end of the cycle.
D a ta W r ite ST 1 SCK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SI
"1 "
"1 "
"1 "
"1 "
"1 "
R,W
RS
"0 "
D7
D6
D5
D4
D3
D2
D1
D0
S y n c h r o n o u s B its S ta rt B y te D a ta R e a d ST W a it T im e : tW 1ms 1 SCK BF "0 " 2 3 4 5 6 7 8
A IT
In s tr u c tio n /D a ta
1
2
3
4
5 6
7
8
9
S I, S O
"1 "
"1 "
"1 "
"1 "
"1 " R , W
RS
"0 "
IR 6
IR 5
IR 4
IR 3
IR 2
IR 1
IR 0
S y n c h r o n o u s B its S ta rt B y te R e a d D a ta
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Commands Instruction Clear display RS 0 R, W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 Description Clear all display, and sets the DDRAM address at 00H. Sets the DDRAM address at 00H. Also returns the display shifted to the original position. The DDRAM contents remain unchanged. Sets the cursor direction and specifies the display shift. These operations are performed during writing/reading data. Sets all display ON/OFF(D), cursor ON/OFF(C), cursor blink of character position (B). Shifts display or cursor, w h i l e ke e p i n g t h e DDRAM contents.
Cursor home
0
0
0
0
0
0
0
0
1
x
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
Display On/Off
0
0
0
0
0
0
1
D
C
B
Cursor or display shift
0
0
0
0
0
1
S/C
R/L
x
x
Function
0
0
0
0
1
DL
N
x
BR1
Sets data length BR0 (in parallel data transfer) and Number of line Sets the address of the CGRAM. After that, data of the DDRAM is transferred. Sets the address of the DDRAM. After that, data of the DDRAM is transferred. Reads the busy flag (BF) and the address counter. BF is output as 0 always. Writes data into the CGRAM of the DDRAM. Reads data from the CGRAM or DDRAM.
CGRAM address set
0
0
0
1
ACG
DDRAM address set
0
0
1
ADD
Read busy flag & address Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM Note:
0
1
BF=0
ACC
1 1
0 1
Write data Read DR data
I/D=1: Increment, I/D=0: Decrement S=1: Display shift enable, S=0: Cursor shift enable S/C=1: Display shift, S/C=0: Cursor shift R/L=1: Right shift, R/L=0: Left shift DL=1: 8bit, DL=0: 4bit BR1, BR0= (00: 100%) , (01: 75%) , (10: 50% ) , (11: 25%) X: Dont care ACG: CGRAM address ADD: DDRAM address ACC: Address counter DDRAM: Display Data RAM CGRAM: Character Generator RAM
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Clear Display
The instruction:
* Fills all locations in the display data RAM (DDRAM) with 20H (Blank character). * Clears the contents of the address counter (ACC) to 00H. * Sets display for zero character shifts (returns to original position). * Sets the address counter to point to the display data RAM (DDRAM). * If cursor is displayed, move cursor to the left most character in the top line (upper line). * Sets address counter (ACC) to increment on each access to DDRAM or CGRAM. When resetting
Cursor Home
The instruction:
* Clears the contents of the address counter (ACC) to 00H. * Sets the address counter to point to the display data RAM (DDRAM). * Sets display for zero character shifts (returns to original position). * If cursor is displayed, move cursor to the left most character in the top line (upper line).
Entry Mode
This instruction selects whether the cursor position increments or decrements after each DDRAM or CGRAM access and determines the direction the information on the display shifts after each DDRAM write. The instruction also enables or disables display shifts after each DDRAM write (information on the display does not shift after a DDRAM read or CGRAM access). The DDRAM, CGRAM, and cursor position are not affected by this instruction. I/D=0: The AC decrements after each DDRAM or CGRAM access. If S=1, the information on the display shifts to the right by one character position after each DDRAM write. I/D=1: The AC increments after each DDRAM or CGRAM access. If S=1, the information on the display shifts to the left by one character position after each DDRAM write. S=0: S=1: The display shift function is disabled. The display shift function is enabled. Cursor Move and Display Shift by the Entry Mode Set I/D 0 1 0 1 S 0 0 1 1 After Writing DDRAM Data Cursor moves one character to the left. Cursor moves one character to the right. After Reading DDRAM Data Cursor moves one character to the right. Cursor moves one character to the right.
Display shifts one character to the right without cursor Cursor moves one character to the left. movements. Display shifts one character to the left without cursor moveCursor moves one character to the right. ments.
When resetting
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Display ON/OFF
This instruction selects whether the display and cursor are on or off and selects whether or not the character at the current cursor position blinks. The DDRAM, CGRAM, and cursor position are not affected by this instruction.
* D=0: The display is off (display blank). * D=1: The display is on (contents of the DDRAM is displayed). * C=0: The cursor is off. * C=1: The cursor is on (8th rows of pixels). * B=0: The blinking character function is disabled. * B=1: The blinking character function is enabled Note: A character with all pixels on will alternate with the character displayed at the current cursor position at a 1Hz rate with a 50% duty cycle.
When resetting
Cursor or Display Shift This instruction shifts the display and/or moves the cursor to the left or right, without reading or writing to the DDRAM. S/C bit selects movement of the cursor or movement of both cursor and display.
* S/C=1: Shift both cursor and display. * S/C=0: Shift only the cursor. R/L bit selects whether moving the direction to the left or right of the display and/or cursor. * R/L=1: Shift one character right. * R/L=0: Shift one character left.
Cursor or Display Shift S/C 0 0 1 1 Function Set R/L 0 1 0 1 Cursor Position Decrements by one (left) Increments by one (right) Decrements by one (left) Increments by one (right) Information on the Display No change No change Shifts on character position to the left Shifts on character position to the right
This instruction sets the width of the data bus for the parallel interface modes, the number of display lines, and the luminance level (brightness) of the VFD. DDRAM, CGRAM, and cursor position are not affected by this instruction.
* DL=0: Sets the data bus width for the parallel interface modes to 4-bit (DB7~DB4). * DL=1: Sets the data bus width for the parallel interface modes to 8-bit (DB7~DB0). * N=0: Sets the number of display lines to 1 (this setting is not recommended). * N=1: Sets the number of display lines to 2
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BR1, BR0 flag is brightness control for the VFD to modulate the pulse width of the segment output as follows. tDSP@200ms, tBLK@10ms BR1 0 0 1 1 BR0 0 1 0 1 Brightness 100% 75% 50% 25% tP tDSP1.00 tDSP0.75 tDSP0.50 tDSP0.25
Note: n means number of grid, T=nx (tDSP+tBLK) When resetting
CGRAM Address Set
This instruction places the 6-bit CGRAM address specified by DB5~DB0 into the cursor position. Subsequent data writes (reads) will be to (from) the CGRAM. The DDRAM and CGRAM contents are not affected by this instruction. When resetting: Dont care.
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DDRAM Address Set
This instruction places the 7-bit DDRAM address specified by DB6~DB0 into the cursor position. Subsequent data writes (reads) will be to (from) the DDRAM. The DDRAM and CGRAM contents are not affected by this instruction. Valid DDRAM Address Ranges Number of Character 1st line 2nd line When resetting: Dont care. Read Busy Flag and Address 40 40 Address Range 00H~27H 40H~67H
This instruction reads the Busy Flag (BF)* and the value of address counter in binary AAAAAAA. This address counter is used by the CGRAM and DDRAM addresses, its value is determined by the previous instruction. The address counter contents are the same as for instructions CGRAM address set and DDRAM address set. Note: * means the Busy Flag (BF) always outputs a 0. Write Data to the CGRAM or DDRAM
This instruction writes the 8-bit data byte on DB7~DB0 into the DDRAM or CGRAM location addressed by the cursor position. The most recent DDRAM or CGRAM Address Set instruction determines whether the write is to the DDRAM or CGRAM. This instruction also increments or decrements the cursor position and shifts the display according to the I/D and S bits set by the Entry Mode Set instruction. Read Data from CGRAM or DDRAM
This instruction reads the 8-bit data byte from the DDRAM or CGRAM location addressed by the cursor position on DB7~DB0. The most recent DDRAM or CGRAM Address Set instruction determines whether the read is from the DDRAM or CGRAM. This instruction also increments or decrements the cursor position and shifts the display according to the I/D and S bits set by the Entry Mode Set instruction. Before sending this instruction, a DDRAM or CGRAM Address Set instruction should be executed to set the cursor position to the desired DDRAM or CGRAM address to be read. After reading one data, the value of the address is automatically increased or decreased by 1 according to the selection by Entry mode. Note: The Address counter is automatically increased or decreased by 1 after a data write instruction to the CGRAM or DDRAM are executed. But at this moment the data to be pointed to by the address counter cannot be read if a data read instruction is executed. Therefore, to read data correctly, executing an address set instruction or cursor shift instruction (the only case of a DDRAM data read) just before reading, or reading the second data in case of reading data continuously by executing a read data instruction.
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Power ON Reset After a power-on reset, the module is initialize to the following conditions:
* All DDRAM locations are set to 20H (character code for a space). * The cursor position is set to DDRAM address 00H * The relationship between DDRAM addresses and character positions on the VFD is set to the non-shifted position. * Entry Mode Set instruction bits:
I/D=1: The cursor position increments after each DDRAM or CGRAM access. If S=1, the information on the display shifts to the left by one character position after each DDRAM write. S=0: The display shift function is disabled.
* Display On/Off Control instruction bits:
D=0: C=0: B=0:
The display is off (display blank). The cursor is off. The blinking character function is disabled.
* Function Set instruction bits:
DL=1: Sets the data bus width for the parallel interface modes to 8 bits (DB7~DB0). N=1: Number of display lines is set to 2. BR1, BR0=0,0: Sets the luminance level to 100%.
* MPU interface, duty ratio selection are based on the following table.
Relationship between Status of HT16514 and Pin Selection at Power on Reset Pin Name TEST 1 0 or open 0 or open 0 or open 0 or open 0 or open 0 or open IM x 0 1 x x x x DS1 DS0 x x x 0 0 1 1 x x x 0 1 0 1 Function Self test mode Serial interface Parallel interface Duty= 1/16 (16C1 or 2L display) Duty= 1/20 (20C1 or 2L display) Duty= 1/24 (24C1 or 2L display) Duty= 1/40 (40C1 or 2L display) Extension driver should be used. The number of line is selected by instruction. Its not necessary to use the extension driver. The number of line is selected by instruction. Remark This is effective on aging. SI, SO, SCK, ST RS, E, R, W, DB7~DB4 or DB7~DB0
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Example (8-bit Data Parallel, Data Increment Mode)
Initialization Sequence & Data Set Initialization Programming Example & Data Set (M68 series MPU) RS R, W D7 D6 D5 D4 D3 D2 D1 D0 Description
Power On Function Set Data length: 8 bits Display line number: 2 lines VFD Brightness: 75% CGRAM address set to 00H
0
0
0
0
1
1
1
x
0
1
0
0
0 x x
1 x x | x 0 D D | D 0
0 x x | x 0 D D | D 0
0 D D | D 0 D D | D 0
0 D D | D 0 D D | D 1
0 D D | D 0 D D | D 1
0 D D | D 0 D D | D 0
0 D D | D 0 D D | D 0
1
0 | x
Write data to CGRAM 64 bytes (8 characters)
0
0
1 D D
DDRAM address set to 00H
1
0 | D
Write data to DDRAM 80 bytes (80 characters)
0
0
Display ON/OFF Display ON, cursor OFF, cursor blink OFF
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Application Circuits
G r id E x te r n a l E x te n s io n D r iv e G 25~G 40
E R S,ST E (R D ), S C K CS R ,W (W R ) S I, S O D S0,D S1 MCU IM MPU D LS R L1,R L2 RESET D B0~D D B7 OSCI OSCO VDD LG N D VH PGND H T16514 G 1~G 24 S1~S80 F SDO SLK CL LE VFD
R
OSC
V
DD
LG ND
V
H
PGND
Note: ROSC=56kW for oscillator resistor
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Package Information
144-pin LQFP (2020) Outline Dimensions
C D 108 73 G H
I 109 72
A
B
F
E
144
37 K 1 36 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 21.9 19.9 21.9 19.9 3/4 3/4 1.35 3/4 3/4 0.45 0.1 0 Nom. 3/4 3/4 3/4 3/4 0.5 0.2 3/4 3/4 0.1 3/4 3/4 3/4 Max. 22.1 20.1 22.1 20.1 3/4 3/4 1.45 1.6 3/4 0.75 0.2 7
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2006 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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